LAYOUT CONSIDERATIONS
As with all high frequency switchers, when considering
layout, care must be taken to achieve optimal electrical,
thermal and noise performance. For maximum efficiency,
switch rise and fall times are typically in the nanosecond
range. To prevent noise both radiated and conducted, the
high speed switching current path, shown in Figure 5,
must be kept as short as possible. This is implemented in
the suggested layout of Figure 6. Shortening this path will
also reduce the parasitic trace inductance of approximately
25nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the LT1961 switch. When
operating at higher currents and output voltages, with
poor layout, this spike can generate voltages across the
LT1961 that may exceed its absolute maximum rating. A
ground plane should always be used under the switcher
circuitry to prevent interplane coupling and overall noise.
The VC and FB components should be kept as far away as
possible from the switch node. The LT1961 pinout has
been designed to aid in this. The ground for these components
should be separated from the switch current path.
Failure to do so will result in poor stability or subharmonic
like oscillation.
回 舅舅大：
Failure to do so will result in poor stability or subharmonic
like oscillation.
這句也只說到差的穩定性或震盪
就只因,在沒搞清楚狀況前,製作新的pcb也是個賭注,不確定100%沒問題！
with poor layout, this spike can generate voltages across the
LT1961 that may exceed its absolute maximum rating.
也許這句話才是重點, 在某種狀況下,可能像SIMON大所講,疊加電壓超過極限值 35v
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發表於 2017-8-30 15:08:22
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