|
發表於 2013-7-21 20:34:54
|
顯示全部樓層
一舨 屛線
1 Reserved Open or High Auo internal test pin
2 Reserved Open or High Auo internal test pin
3 Reserved Open or High Auo internal test pin
4 GND Ground and Signal Return
5 RIN0- LVDS Channel 0 negative
6 RIN0+ LVDS Channel 0 positive
7 GND Ground and Signal Return for LVDS
8 RIN1- LVDS Channel 1 negative
9 RIN1+ LVDS Channel 1 positive
10 GND Ground and Signal Return for LVDS
11 RIN2- LVDS Channel 2 negative
12 RIN2+ LVDS Channel 2 positive
13 GND Ground and Signal Return for LVDS
14 RCLK- LVDS Clock negative
15 RCLK+ LVDS Clock positive
16 GND Ground and Signal Return for LVDS
17 RIN3- LVDS Channel 3 negative
18 RIN3+ LVDS Channel 3 positive
19 GND Ground and Signal Return
20 Reserved Open or High Auo internal test pin
21 LVDS Option Low for JEIDA, High/Open for NS
22 Reserved Open
23 GND Ground and Signal Return
24 GND Ground and Signal Return
25 GND Ground and Signal Return
26 Vcc 5V, DC, Regulated
27 Vcc 5V, DC, Regulated
28 Vcc 5V, DC, Regulated
29 Vcc 5V, DC, Regulated
30 Vcc 5V, DC, Regulated |
評分
-
2
查看全部評分
-
|