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發表於 2020-4-4 12:18:38
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程式專案內容不丟懶人包，請自行慢慢收集……
原本找不到 startup_stm32f0xx.s，所以抓了另一個檔案改一改。
startup_stm32f0xx.s 內容，RESET 後的第一行以及中斷向量表：
- ;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
- ;* File Name : startup_stm32f40x.s
- ;* Author : MCD Application Team
- ;* Version : V0.0.2
- ;* Date : 25-July-2011
- ;* Description : STM32F40x devices vector table for EWARM toolchain.
- ;* This module performs:
- ;* - Set the initial SP
- ;* - Set the initial PC == _iar_program_start,
- ;* - Set the vector table entries with the exceptions ISR
- ;* address.
- ;* After Reset the Cortex-M4 processor is in Thread mode,
- ;* priority is Privileged, and the Stack is set to Main.
- ;********************************************************************************
- ;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- ;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
- ;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
- ;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
- ;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
- ;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- ;*******************************************************************************/
- ;
- ;
- ; The modules in this file are included in the libraries, and may be replaced
- ; by any user-defined modules that define the PUBLIC symbol _program_start or
- ; a user defined start symbol.
- ; To override the cstartup defined in the library, simply add your modified
- ; version to the workbench project.
- ;
- ; The vector table is normally located at address 0.
- ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
- ; The name "__vector_table" has special meaning for C-SPY:
- ; it is where the SP start value is found, and the NVIC vector
- ; table register (VTOR) is initialized to this address if != 0.
- ;
- ; Cortex-M version
- ;
- MODULE ?cstartup
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
- SECTION .intvec:CODE:NOROOT(2)
- EXTERN __iar_program_start
- EXTWEAK __iar_init_vfp
- EXTERN SystemInit
- PUBLIC __vector_table
- DATA
- __vector_table
- DCD sfe(CSTACK) ; Reserved @ 0x0000 0000
- DCD Reset_Handler ; Reset Handler @ 0x0000 0004
- DCD NMI_Handler ; NMI Handler @ 0x0000 0008
- DCD HardFault_Handler ; Hard Fault Handler @ 0x0000 000c
- DCD MemManage_Handler ; Reserved @ 0x0000 0010
- DCD BusFault_Handler ; Reserved @ 0x0000 0014
- DCD UsageFault_Handler ; Reserved @ 0x0000 0018
- DCD 0 ; Reserved @ 0x0000 001c
- DCD 0 ; Reserved @ 0x0000 0020
- DCD 0 ; Reserved @ 0x0000 0024
- DCD 0 ; Reserved @ 0x0000 0028
- DCD SVC_Handler ; SVCall Handler @ 0x0000 002c
- DCD DebugMon_Handler ; Reserved @ 0x0000 0030
- DCD 0 ; Reserved @ 0x0000 0034
- DCD PendSV_Handler ; PendSV Handler @ 0x0000 0038
- DCD SysTick_Handler ; SysTick Handler @ 0x0000 003c
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog @ 0x0000 0040
- DCD 0 ; Reserved
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line[1:0]
- DCD EXTI2_3_IRQHandler ; EXTI Line[3:2]
- DCD EXTI4_15_IRQHandler ; EXTI Line[4:15]
- DCD 0 ; Reserved
- DCD DMA_CH1_IRQHandler ; DMA CH1
- DCD DMA_CH2_3_IRQHandler ; DMA CH2/3
- DCD DMA_CH4_5_IRQHandler ; DMA CH4/5
- DCD ADC_IRQHandler ; ADC
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler
- DCD TIM1_CC_IRQHandler ; TIM1
- DCD 0 ; Reserved
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_IRQHandler ; TIM6
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler
- DCD TIM15_IRQHandler
- DCD TIM16_IRQHandler
- DCD TIM17_IRQHandler
- DCD I2C1_IRQHandler
- DCD I2C2_IRQHandler
- DCD SPI1_IRQHandler
- DCD SPI2_IRQHandler
- DCD USART1_IRQHandler
- DCD USART2_IRQHandler
- DCD USART3_4_5_6_IRQHandler
- DCD 0
- DCD USB_IRQHandler
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ;;
- ;; Default interrupt handlers.
- ;;
- THUMB
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER:NOROOT(2)
- Reset_Handler
- FUNCALL Reset_Handler, __iar_init_vfp ; Enable VFP if it is enabled in the project settings
- BL __iar_init_vfp
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
- PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- NMI_Handler
- B NMI_Handler
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- HardFault_Handler
- B HardFault_Handler
- PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- MemManage_Handler
- B MemManage_Handler
- PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- BusFault_Handler
- B BusFault_Handler
- PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- UsageFault_Handler
- B UsageFault_Handler
- PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- SVC_Handler
- B SVC_Handler
- PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- DebugMon_Handler
- B DebugMon_Handler
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- PendSV_Handler
- B PendSV_Handler
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
- SysTick_Handler
- B SysTick_Handler
- ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
- ;;
- ;; peripheral interrupt handlers.
- ;;
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- WWDG_IRQHandler
- B WWDG_IRQHandler
- PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- RTC_WKUP_IRQHandler
- B RTC_WKUP_IRQHandler
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- FLASH_IRQHandler
- B FLASH_IRQHandler
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- RCC_IRQHandler
- B RCC_IRQHandler
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
- PUBWEAK DMA_CH1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- DMA_CH1_IRQHandler
- B DMA_CH1_IRQHandler
- PUBWEAK DMA_CH2_3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- DMA_CH2_3_IRQHandler
- B DMA_CH2_3_IRQHandler
- PUBWEAK DMA_CH4_5_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- DMA_CH4_5_IRQHandler
- B DMA_CH4_5_IRQHandler
- PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- ADC_IRQHandler
- B ADC_IRQHandler
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM3_IRQHandler
- B TIM3_IRQHandler
- PUBWEAK TIM6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM6_IRQHandler
- B TIM6_IRQHandler
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM14_IRQHandler
- B TIM14_IRQHandler
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM15_IRQHandler
- B TIM15_IRQHandler
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM16_IRQHandler
- B TIM16_IRQHandler
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- TIM17_IRQHandler
- B TIM17_IRQHandler
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- I2C1_IRQHandler
- B I2C1_IRQHandler
- PUBWEAK I2C2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- I2C2_IRQHandler
- B I2C2_IRQHandler
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- SPI1_IRQHandler
- B SPI1_IRQHandler
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- SPI2_IRQHandler
- B SPI2_IRQHandler
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- USART1_IRQHandler
- B USART1_IRQHandler
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- USART2_IRQHandler
- B USART2_IRQHandler
- PUBWEAK USART3_4_5_6_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- USART3_4_5_6_IRQHandler
- B USART3_4_5_6_IRQHandler
- PUBWEAK USB_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
- USB_IRQHandler
- B USB_IRQHandler
- END
- /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
system_stm32f0xx.c：
這個檔案可有可無，主要是在 startup_stm32f0xx.s 裡有一個 call SystemInit() 的動作，裡面其實也沒有什麼，直接註解掉也是可以跑。
- /**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F0xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© Copyright (c) 2016 STMicroelectronics.
- * All rights reserved.</center></h2>
- *
- * This software component is licensed by ST under BSD 3-Clause license,
- * the "License"; You may not use this file except in compliance with the
- * License. You may obtain a copy of the License at:
- * opensource.org/licenses/BSD-3-Clause
- *
- ******************************************************************************
- */
- /** @addtogroup CMSIS
- * @{
- */
- /** @addtogroup stm32f0xx_system
- * @{
- */
- /** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
- //#include "stm32f0xx.h"
- #include <ST/iostm32f051x4.h>
- /**
- * @}
- */
- /** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
- /**
- * @}
- */
- /** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
- #if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
- #endif /* HSE_VALUE */
- #if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
- #endif /* HSI_VALUE */
- #if !defined (HSI48_VALUE)
- #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
- #endif /* HSI48_VALUE */
- /**
- * @}
- */
- /** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
- /**
- * @}
- */
- /** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
- //uint32_t SystemCoreClock = 8000000;
- //const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
- //const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
- /**
- * @}
- */
- /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
- /**
- * @}
- */
- /** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
- /**
- * @brief Setup the microcontroller system.
- * Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
- #ifndef uint32_t
- typedef unsigned int uint32_t;
- #endif
- void SystemInit(void)
- {
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC_CR |= (uint32_t)0x00000001U;
- #if defined (STM32F051x8) || defined (STM32F058x8)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC_CFGR &= (uint32_t)0xF8FFB80CU;
- #else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC_CFGR &= (uint32_t)0x08FFB80CU;
- #endif /* STM32F051x8 or STM32F058x8 */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC_CR &= (uint32_t)0xFEF6FFFFU;
- /* Reset HSEBYP bit */
- RCC_CR &= (uint32_t)0xFFFBFFFFU;
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC_CFGR &= (uint32_t)0xFFC0FFFFU;
- /* Reset PREDIV[3:0] bits */
- RCC_CFGR2 &= (uint32_t)0xFFFFFFF0U;
- #if defined (STM32F072xB) || defined (STM32F078xx)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFCFE2CU;
- #elif defined (STM32F071xB)
- /* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFCEACU;
- #elif defined (STM32F091xC) || defined (STM32F098xx)
- /* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC_CFGR3 &= (uint32_t)0xFFF0FEACU;
- #elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
- /* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
- RCC_CFGR3 &= (uint32_t)0xFFFFFEECU;
- #elif defined (STM32F051x8) || defined (STM32F058xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
- RCC_CFGR3 &= (uint32_t)0xFFFFFEACU;
- #elif defined (STM32F042x6) || defined (STM32F048xx)
- /* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
- RCC_CFGR3 &= (uint32_t)0xFFFFFE2CU;
- #elif defined (STM32F070x6) || defined (STM32F070xB)
- /* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
- RCC_CFGR3 &= (uint32_t)0xFFFFFE6CU;
- /* Set default USB clock to PLLCLK, since there is no HSI48 */
- RCC_CFGR3 |= (uint32_t)0x00000080U;
- #else
- RCC_CFGR3 = (uint32_t)0;
- // #warning "No target selected"
- #endif
- /* Reset HSI14 bit */
- RCC_CR2 &= (uint32_t)0xFFFFFFFEU;
- /* Disable all interrupts */
- RCC_CIR = 0x00000000U;
- }
- #if 0
- /**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
- void SystemCoreClockUpdate (void)
- {
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
- SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
- }
- #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
- else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
- {
- /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
- SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
- }
- #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
- else
- {
- #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
- || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
- || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
- /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
- SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
- #else
- /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
- STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
- STM32F091xC || STM32F098xx || STM32F030xC */
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
- }
- #endif
- /**
- * @}
- */
- /**
- * @}
- */
- /**
- * @}
- */
- /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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