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發表於 2010-4-7 15:12:04
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回復 5# 的帖子
G1/S3- Cold Suspend to RAM (STR). Context saved to memory.
G1/S3-Hot Suspend to RAM (STR). All voltage supplies left on except the CPU Core and FSB VTT
S3 Hot - The S3-Hot state keeps more of the platform logic, including the ICH7
core well, powered in the S3 state to reduce the cost of external power plane logic.
When implementing S3 HOT on the platform SLP_S3# is only used to remove power to
the processor and to shut system clocks. This impacts the board design, but there is no
specific ICH7 bit or strap needed to indicate which option is selected.
Note: When implementing S3 Hot; the SLP_S4# signal is used to cut power to the ICH7 core
well in addition to power to the memory. |
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